/*
 * Arm SCP/MCP Software
 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef INTERNAL_REG_PPU_H
#define INTERNAL_REG_PPU_H

#define PPU_BASE_AP 0x54120000
#define PPU_BASE_SCP 0x48120000

#define PPU_BASE PPU_BASE_SCP

#define PPU_PPR_OFFSET 0x000
#define PPU_PSR_OFFSET 0x004
#define PPU_PCR_OFFSET 0x00C

#define PPU0_BASE (PPU_BASE + 0x000)
#define PPU1_BASE (PPU_BASE + 0x020)
#define PPU2_BASE (PPU_BASE + 0x040)
#define PPU3_BASE (PPU_BASE + 0x060)
#define PPU4_BASE (PPU_BASE + 0x080)
#define PPU5_BASE (PPU_BASE + 0x0A0)
#define PPU6_BASE (PPU_BASE + 0x0C0)
#define PPU7_BASE (PPU_BASE + 0x0E0)
#define PPU8_BASE (PPU_BASE + 0x100)

#define PPU0_PPR (PPU0_BASE + PPU_PPR_OFFSET)
#define PPU0_PSR (PPU0_BASE + PPU_PSR_OFFSET)
#define PPU0_PCR (PPU0_BASE + PPU_PCR_OFFSET)
#define PPU1_PPR (PPU1_BASE + PPU_PPR_OFFSET)
#define PPU1_PSR (PPU1_BASE + PPU_PSR_OFFSET)
#define PPU1_PCR (PPU1_BASE + PPU_PCR_OFFSET)
#define PPU2_PPR (PPU2_BASE + PPU_PPR_OFFSET)
#define PPU2_PSR (PPU2_BASE + PPU_PSR_OFFSET)
#define PPU2_PCR (PPU2_BASE + PPU_PCR_OFFSET)
#define PPU3_PPR (PPU3_BASE + PPU_PPR_OFFSET)
#define PPU3_PSR (PPU3_BASE + PPU_PSR_OFFSET)
#define PPU3_PCR (PPU3_BASE + PPU_PCR_OFFSET)
#define PPU4_PPR (PPU4_BASE + PPU_PPR_OFFSET)
#define PPU4_PSR (PPU4_BASE + PPU_PSR_OFFSET)
#define PPU4_PCR (PPU4_BASE + PPU_PCR_OFFSET)
#define PPU5_PPR (PPU5_BASE + PPU_PPR_OFFSET)
#define PPU5_PSR (PPU5_BASE + PPU_PSR_OFFSET)
#define PPU5_PCR (PPU5_BASE + PPU_PCR_OFFSET)
#define PPU6_PPR (PPU6_BASE + PPU_PPR_OFFSET)
#define PPU6_PSR (PPU6_BASE + PPU_PSR_OFFSET)
#define PPU6_PCR (PPU6_BASE + PPU_PCR_OFFSET)
#define PPU7_PPR (PPU7_BASE + PPU_PPR_OFFSET)
#define PPU7_PSR (PPU7_BASE + PPU_PSR_OFFSET)
#define PPU7_PCR (PPU7_BASE + PPU_PCR_OFFSET)
#define PPU8_PPR (PPU8_BASE + PPU_PPR_OFFSET)
#define PPU8_PSR (PPU8_BASE + PPU_PSR_OFFSET)
#define PPU8_PCR (PPU8_BASE + PPU_PCR_OFFSET)
#define PPU_HWCACTIVE_SR (PPU_BASE + 0x800)
#define PPU_WFI_WFE_SR (PPU_BASE + 0x804)
#define PPU_PID_4 (PPU_BASE + 0xFD0)
#define PPU_PID_0 (PPU_BASE + 0xFE0)
#define PPU_PID_1 (PPU_BASE + 0xFE4)
#define PPU_PID_2 (PPU_BASE + 0xFE8)
#define PPU_PID_3 (PPU_BASE + 0xFEC)
#define PPU_COMP_ID0 (PPU_BASE + 0xFF0)
#define PPU_COMP_ID1 (PPU_BASE + 0xFF4)
#define PPU_COMP_ID2 (PPU_BASE + 0xFF8)
#define PPU_COMP_ID3 (PPU_BASE + 0xFFC)

#endif /* INTERNAL_REG_PPU_H */
